In general, it is believed that EST's are used as circuit breakers in the range of a few hundred to a few thousand volt blocking voltage. The use of such EST's as ignition transistor, i.e. as switch on the primary side of an ignition coil is of particular interest.
It is believed that the structure of the EST comes about from that of available V-IGBT's (vertical insulated gate bipolar transistor) by adding additional floating emitter structures, shielded by diffusion regions, on the upper side of the chip. The advantage of EST's compared to V-IGBT's is generally seen in better forward current behavior, i.e. a lower voltage drop in the switched-on state. As in the case of V-IGBT, the terminal connected to the reverse side emitter is denoted as the anode, the gate terminal as the gate, and the connection to the source and body diffusions as the cathode.
As is purportedly discussed in B. J. Baliga, Power Semiconductor Devices, PWS Publishing Company, Boston 1995, pp. 543–568, with regard to the design of MOS control heads, there are essentially two types of EST, whose active area is made up of a plurality of parallel connected strip-shaped or cell-shaped MOS control heads and floating emitter structures.
The first type is the so-called single channel EST (SC-EST), whose half cell cross section 100 is shown in FIGS. 7 and 9. The second type is the so-called dual channel EST (DC-EST), whose half cell cross section 200 is shown in FIGS. 8 and 10.
As in the V-IGBT, with respect to the design of the emitter on the reverse side of the chip, there are essentially two types, the punch-through type (PT type) whose half cell cross section 300 is shown in FIGS. 9 and 10, and the non-punch-through type (NPT type), whose half cell cross section 400 is shown in FIGS. 7 and 8,
Thus there are therefore the following four basic types of vertical EST's, made up of the combination of these described design possibilities: the SC-NPT EST (FIG. 7), the SC-PT EST (FIG. 9), the DC-NPT EST (FIG. 8) and the DC-PT EST (FIG. 10).
Referring to FIG. 7, the functioning procedure in the forward current case is the following for the SC-NPT EST.
In this SC-NPT EST, gate 103, usually made of polysilicon, is composed, per half cell, of two parts which are connected to each other via the third dimension (not shown). The gate, which is insulated from the semiconductor only by a thin gate oxide layer 109, is brought to a potential above the voltage level of MOS control heads 106, 107, 108, 160, 180 with respect to cathode 101, whose metallization is at a reference potential. Intermediate oxide layer 110 is used for insulating cathode 101 from gate 103. Thereupon, in the region of the p-type areas (p-type body area 108, p-type area 180), inversion channels are generated at the HL semiconductor surface under gate 103, and the semiconductor surface is brought into accumulation in the vicinity of n−-doped drift zone 104. In the case of the positive anode voltage at the metallization of anode 102 on the back of the chip with respect to cathode 101, electrons are injected via n+-regions 106, 160, the electrostatically induced MOS channels and the accumulation layer into n−-drift zone 104. Thereupon p+-doped emitter 105 on the anode side injects holes into n−-drift zone 104, which leak away via p-regions 180, 108 and p+-contact region 107 to cathode 101.
Beginning at a certain current density, because of the lateral voltage drop caused by the hole current proportion in p-region 180, the p-n junction between n+-region 160 and p-region 180 is polarized in the forward direction, whereby electrons are injected transversely via p-region 180 into drift zone 104 from n+-region 160 currently acting as an emitter, without first having to pass the MOS channel lying under the right-hand gate part.
The now active four-layer structure made up of n+-region 160, p-region 180, n−-drift zone 104 and p+-emitter 105 on the reverse side, acts as a thyristor whose n+-emitter 160 is supplied with electrons via n+-region 106 and the MOS channel formed under the left-hand part of gate 103, and thus may be switched or controlled with the aid of gate 103.
As compared to a normal thyristor, the EST accordingly has the advantage that, by the drop in the gate cathode voltage below the threshold voltage, it can be turned off and the current flowing through it is controllable by the gate voltage. Its forward current characteristic curve thus shows a current saturation range.
In forward current operation, n−-drift zone 104 is flooded in such a way by charge carriers that its conductivity is increased. At the usual forward current densities it is at high-level injection. Intermediate oxide layer 110 is used for insulating cathode 101 from gate 103.
The method of functioning of SC-PT EST 300, shown in FIG. 9, in the forward current case is analogous to the SC-NPT EST. In the SC-PT EST an additional n-buffer layer 150 is present, whose function will be explained in connection with the blocking case. Because of n-buffer layer 150 it is possible to reduce the thickness of n−-drift zone 104, in order to achieve better forward current characteristics. The SC-PT EST may be produced, for example, on a p+-substrate having an emitter 105 on the reverse side, n-buffer layer 150 and n−-drift zone 104 being grown epitaxially on this p+-substrate.
The method of functioning of DC-PT EST 200, as in FIG. 8, in the forward current case is similar to that of SC-PT EST 300 as in FIG. 9.
In the case of DC-PT EST 200, gate 103, which is usually made of polysilicon, has only one part per half cell. Gate 103, insulated from the semiconductor surface only by a thin gate oxide layer 109 is brought to a potential above the voltage level of MOS control heads 106, 107, 108, 160, 180 with respect to cathode 101, whose metallization is at a reference potential. Thereupon, in the region of the p-type areas (p-type body area 108, p-type area 180), inversion channels are generated under gate 103, and the semiconductor surface is brought into accumulation in the vicinity of n−-doped drift zone 104. In the case of the positive anode voltage at the metallization of anode 102 on the back of the chip with respect to cathode 101, electrons are injected via n+-regions 106, the left-hand electrostatically induced MOS channels and the accumulation layer into n-drift zone 104. Thereupon p+-doped emitter 105 on the anode side injects holes into n−-drift zone 104, which leak away, on the one hand via p+-contact region 107 and p-body region 108, and on the other hand via p+-contact region 107 and via p-zones 180, 108 and the part of drift zone 104 lying between them, to cathode 101. Beginning at a certain current density, because of the lateral voltage drop caused by the hole current proportion in p-region 180 and the laterally bordering part of n-drift zone 104, the p-n junction between n+-region 160 and p-region 180 is polarized in the flow direction, whereby electrons are injected transversely via p-region 180 into n-drift zone 104 from n+-region 160 currently acting as an emitter, after first passing the MOS channels and the accumulation layer lying under the gate.
The now active four-layer structure made up of n+-region 160, p-region 180, n−-drift zone 104 and p+-emitter 105 on the reverse side, acts as a thyristor whose n+-emitter 160 is supplied with electrons via n+-region 106 and the channel formed under gate 103, and thus may be switched or controlled with the aid of the gate.
In forward current operation, n−-drift zone 104 is flooded in such a way by charge carriers that its conductivity is increased. At the usual forward current densities it is at high-level injection.
Compared to the single channel EST's described farther above, dual channel EST's have the advantage of a further extended, secure working range in the forward direction (FBSOA).
The method of functioning of DC-PT-NPT, as in FIG. 10, is completely analogous to the DC-NPT EST. In the DC-PT EST, additional n-buffer layer 150 is present, whose function will be explained in connection with the blocking case. Because of n-buffer layer 150 it is possible to reduce the thickness of n−-drift zone 104, in order to optimize forward current characteristics. A DC-PT EST may be manufactured analogously to the SC-PT EST.
In the blocking case, in the case of the SC-NT EST as in FIG. 7 and the DC-NPT EST as in FIG. 8, gate 103 is brought to a voltage below the threshold voltage level compared to cathode 101. If anode 102 is now brought to a positive potential, the space charge region developed at the border between p-regions 108, 180 and n−-drift zone 104 expands almost exclusively into n−-drift zone 104. The thickness of n−-drift zone 104 is selected to be greater than the width the space charge region has at a given maximum blocking ability of the component, which is substantially determined by the drift region doping. This leads to the triangular pattern of the electrical field strength |E| along the y-coordinate, indicated in FIG. 7 and FIG. 8. In this context, the maximum of the field strength is in the range of MOS control heads 106, 107, 108, 160, 180.
The blocking case for the SC-PT EST as in FIG. 9 and the DC-PT EST as in FIG. 10 may be described as follows. In these PT EST's, the thickness of the n−-drift zone 104 is selected to be smaller than the width the space charge region has at a given maximum blocking capability of the component. In order to prevent accumulation of the space charge region onto p+-emitter 105 and a current flow connected thereto, n-doped buffer zone 150 is incorporated here with the aim of avoiding the punch-through. This leads to the trapeze-shaped pattern of the electrical field strength |E| along the y-coordinate, indicated in FIG. 9 and FIG. 10. The maximum of the field strength is here, too, in the range of MOS control heads 106, 107, 108, 160, 180. Besides preventing punch-through, n-buffer zone 150 also makes possible the setting of the emitter efficiency, and thereby the forward current behavior and the switching behavior of the PT EST's.
The fact that the field maximum lies in the range of MOS control heads 106, 107, 108, 160, 180, is of disadvantage for the several applications so that it would be helpful to optimize the unfavorable field strength distribution using suitable measures.
German Patent No. 198 16 448 purportedly relates to a general purpose semiconductor wafer for high voltage components such as V-IGBT's, in which on an n-doped semiconductor substrate, at least one n-doped epitaxial layer is provided. A plurality of floating, p-doped semiconductor regions are embedded in the border areas between the substrate and the at least one epitaxial layer, which are dimensioned in such a way that the dimension size of a floating region is small compared to the layer thickness of the at least one epitaxial layer, and is approximately equivalent to the distance between the floating regions in a border area, or smaller. In this context, the floating regions lying in one plane can be connected to one another so that they form a lattice. In the example of the V-IGBT, one assumes that, in the active region of the V-IGBT, when a blocking voltage is applied, the charge carriers are not completely depleted from the floating p-regions.
German Patent No. 198 40 032 refers to a MOS transistor (e.g. an n-channel V-DMOS) having a non-floating compensating structure in the n-drift zone. The compensating structure and/or the n-drift region are doped in such a way that the degree of compensation toward the depth of the component changes in monotone fashion (continuously or stepwise) as follows. During passing of the compensation structure from source to drain, on the source side the p-doping dose outbalances the n-doping dose, whereas at the drain side end of the compensating structure the n-doping dose outbalances the p-doping dose. Under a blocking voltage, a hump-shaped field distribution sets in which has its maximum approximately in the middle of the vertical extension of the compensation structure, where n-doping dose and p-doping dose are exactly compensating. Between the drain-side end of the compensating structure and the n-substrate, a low-doped n-layer may optionally be positioned. In each case the purpose is an increased process security and a heightened robustness in the breakdown.
German Published Patent Application No. 196 04 043 purportedly refers to influencing the field distribution in an MOS transistor or a V-IGBT with the aid of n-doped and p-doped regions embedded in the drift zone, in order to reduce the forward current voltage drop at a given blocking capability. In this context, the overall quantity of the doping of the embedded n-regions is approximately equal to the overall quantity of the doping of the embedded p-regions. The embedded regions, in this case, may be statistically distributed or configured as ball-shaped, strip-shaped or thread-shaped regions, and may be embedded pairwise. Their distance apart may be greater than, or equal to zero, but less than the space charge region. The p-regions are designed to be floating. In the case of statistically distributed p-regions and n-regions, the average concentration of the distributed p-regions are of equal or greater size than that of the embedded n-regions.
For manufacturing, a method is proposed which, beginning with a raw wafer, generates the p-doped and n-doped regions in the n-drift zone by a multiple sequence of epitaxy, implantation and diffusion.
FIG. 11 shows what is believed to be a typical circuit topology used for IGBT's in ignition applications, which would also be suitable for EST's. If one were to use an EST as previously described in such a topology as the switching element, there may be difficulties with the pulse stability of the component. These problems will be described after a brief explanation of the functionality of the circuit.
In the ignition application, a switching element 900 having a typical blocking capability of 400–600 V and connections cathode 901, anode 902 and gate 903 is connected to battery voltage 911 via an ignition coil 912. On the secondary side of ignition coil 912 a spark plug 913 is connected. Diode 904 is used for protection of the EST, and optionally present diode 906 prevents current flow from gate to anode, in the forward current case. Resistors 907, 914, having, for example R907 of approximately 1 kΩ and R914 in the range of 10 to 25 kΩ, define the input resistance of the apparatus, and on the other hand, generate the load of clamping diode 905, which, when IGBT's are used as switching elements is usually designed as a string of polysilicon Zener diodes polarized in the blocking direction. Elements 904, 905, 906, 907, 914 are usually monolithically integrated, with the diodes 904, 906 normally being made of polysilicon.
The circuit configuration is directly operable by a control unit via control terminal 908. For this, a positive voltage such as 5V is connected to 908, whereupon a conducting path is opened between electrodes 901, 902 of the switching element and a current increase through the ignition coil is initiated. At a certain point, the voltage at control terminal 908 is reduced to about 0 V, whereupon the conducting path between electrodes 901, 902 of the switching element vanishes, and the voltage at nodes 902, 909 rises steeply. The voltage increase is transformed upward onto the secondary side of ignition coil 912 and leads to an ignition spark at spark plug 913. Clamping diode 905 has the task of limiting the voltage increase at anode 902 to the so-called clamping voltage of approximately 400 V, so as to protect the switching element and the remaining circuit components. This is particularly important in the so-called pulse case.
This comes up when, for example, no ignition spark is generated as a result of an ignition cable having fallen off. Then switching element 900 must absorb the energy otherwise converted to the spark. Without a voltage limitation, the anode voltage would rise in this case at nodes 902, 909 up to the breakdown of the switching element, and would destroy it. This is prevented by the use of clamping diode 905 in that when a preselected clamping voltage of the switching element is reached, it drives via the control terminal just strongly enough that the exceeding of the clamping voltage at 902, 909 is avoided. Still, because of the high converted energy, this operating case represents a great demand on the pulse stability of the switching element, which cannot always be guaranteed in sufficient measure. The result is the destruction of the switching element.
When an EST as the switching element in the pulse case, the space charge region acquires the entire n-drift zone 104. Via a controlled activation of gate 103 using clamping diodes 905, 906, electrons are injected into the drift zone, via the developed MOS channel, which control p+-emitter 105. As a result of the high current density, the high electrical field strength and thus of the high power loss in the region of the MOS control heads, the component becomes very hot, especially at the cathode, whereupon an electron leakage current from the MOS control heads comes about. The electrons run in the direction of the anode and drive high p+-emitter 105. Thus, they act as an additional drive of the EST. In order to keep the voltage to the value of the clamping voltage, the control of gate 103 is correspondingly reduced via clamping diode 905.
Under certain operating conditions, the driving by the thermally conditioned electron leakage current is so strong that the EST can carry the load current without the gate being driven high (this is favored especially when the emitter efficiency increases with increasing temperature). The controllability of the EST is lost, the temperature continues to increase, and the leakage current continues to increase. Finally, a thermal feedback comes about, and the EST may be destroyed.